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Bit
Name
Reset
Access
Description
Value
1
2
3
Mode
POSEDGE
NEGEDGE
BOTHEDGES
Description
A one HFPERCLK cycle pulse is generated for every positive edge of the incoming
signal
A one HFPERCLK clock cycle pulse is generated for every negative edge of the
incoming signal
A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal
23:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
21:16
SOURCESEL
0x00
RW
Source Select
Select input source to PRS channel.
Value
0b000000
0b000001
0b000010
0b000011
0b000110
0b001000
0b010000
0b010001
0b010010
0b011100
0b011101
0b011110
0b101000
0b101001
0b110000
0b110001
Mode
NONE
VCMP
ACMP0
ACMP1
DAC0
ADC0
USART0
USART1
USART2
TIMER0
TIMER1
TIMER2
RTC
UART0
GPIOL
GPIOH
Description
No source selected
Voltage Comparator
Analog Comparator 0
Analog Comparator 1
Digital to Analog Converter 0
Analog to Digital Converter 0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
Universal Synchronous/Asynchronous Receiver/Transmitter 1
Universal Synchronous/Asynchronous Receiver/Transmitter 2
Timer 0
Timer 1
Timer 2
Real-Time Counter
Universal Asynchronous Receiver/Transmitter 0
General purpose Input/Output
General purpose Input/Output
15:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2:0
SIGSEL
0x0
RW
Signal Select
Select signal input to PRS channel.
Value
SOURCESEL = 0b000000 (NONE)
0bxxx
SOURCESEL = 0b000001 (VCMP)
0b000
SOURCESEL = 0b000010 (ACMP0)
0b000
SOURCESEL = 0b000011 (ACMP1)
0b000
SOURCESEL = 0b000110 (DAC0)
0b000
0b001
SOURCESEL = 0b001000 (ADC0)
0b000
0b001
Mode
OFF
VCMPOUT
ACMP0OUT
ACMP1OUT
DAC0CH0
DAC0CH1
ADC0SINGLE
ADC0SCAN
Description
Channel input selection is turned off
Voltage comparator output VCMPOUT
Analog comparator output ACMP0OUT
Analog comparator output ACMP1OUT
DAC ch0 conversion done DAC0CH0
DAC ch1 conversion done DAC0CH1
ADC single conversion done ADC0SINGLE
ADC scan conversion done ADC0SCAN
SOURCESEL
(USART0)
=
0b010000
0b000
0b001
0b010
USART0IRTX
USART0TXC
USART0RXDATAV
USART 0 IRDA out USART0IRTX
USART 0 TX complete USART0TXC
USART 0 RX Data Valid USART0RXDATAV
SOURCESEL
(USART1)
=
0b010001
0b001
0b010
USART1TXC
USART1RXDATAV
USART 1 TX complete USART1TXC
USART 1 RX Data Valid USART1RXDATAV
SOURCESEL
(USART2)
=
0b010010
2011-04-12 - d0001_Rev1.10
132
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